Grup de Sistemes Electrònics (GSE)
Publicacions en revistes
- Villacorta, H.; Champac, V.; Bota, S.; Segura, J, "Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test", "Microelectronics Reliability", Volum 52, Número 11, Pàgines 2799-2804, 2012. Article.
- Merino, J.L.; Bota, S.A.; Picos, R.; Segura, J, "Alternate characterization technique for static random?access memory static noise margin determination", "International Journal of Circuit Theory and Applications", Volum 41, Número 10, Pàgines 1085-1096, 2012. Article.
- Champac V.; Hernandez, J.V.; Barcelo, S.; Gomez, R.; Hawkins, C.; Segura, J., "Testing of Stuck-Open Faults in Nanometer Technologies", "IEEE Design & Test of Computers", Volum 29, Número 4, Pàgines 80-91, 2012. Article.
- Gili, X.; Barcelo, S.; Bota, S. A.; Segura, J., "Analytical Modeling of Single Event Transients Propagation in Combinational Logic Gates", "IEEE Transactions on Nuclear Science", Volum 59, Número 4, Pàgines 971-979, 2012. Article.